线程束、通道与掩码

The GPU does not schedule threads one by one. It groups them into a warp of 32 threads that march together, executing the same instruction in lockstep.

On NVIDIA hardware a warp is always 32 threads. It is the real unit of execution, so good kernels think in groups of 32, not single threads.

Inside a warp, every thread has a position from 0 to 31 called its lane. The lane id is how warp primitives know who is talking to whom.

You can read the lane directly from a special register instead of computing it. The laneid register always holds 0 through 31 for the current thread.

Threads share one program counter per warp. When an if sends lanes down different paths, the warp diverges and runs each path in turn, hurting speed.

Not every lane is always running. A 32-bit mask marks which lanes are active right now, with one bit per lane set to 1 when that lane participates.

After divergence only some lanes are live. Warp primitives need to know exactly who is present, so you pass them an active mask to stay correct.

When you are sure all 32 lanes are active, the mask is 0xffffffff, every bit set. This full mask is the most common value you will pass.

Inside a branch, do not guess the mask. Call activemask to capture exactly which lanes reached this point right now.

The big win is that lanes in one warp can swap data directly through registers. No shared memory and no barriers are needed for warp-local exchange.

The sync suffix on these intrinsics is a warp-level handshake, not a block barrier. It only coordinates the lanes named in the mask you give it.

Recall what a warp is and how big it is on NVIDIA GPUs.

A warp is 32 lanes running in lockstep, and a mask tracks who is active. That foundation lets lanes share data fast. Next: shuffles for reductions. ✨