Le contrôleur d’interruptions programmable (PIC) et APIC

The CPU has only a single hardware interrupt pin (INTR), yet a PC has dozens of devices that need attention. A dedicated chip multiplexes these IRQ lines onto that one pin and tells the CPU which device fired.

That chip is the Programmable Interrupt Controller (PIC).

The classic PC uses two cascaded 8259A chips, giving 15 usable IRQ lines (IRQ0-IRQ15). The master handles IRQ0-7, the slave IRQ8-15 connected through IRQ2.

• IRQ0 = system timer
• IRQ1 = keyboard
• IRQ14/15 = ATA disks

Each PIC is programmed through two I/O ports:

• Master: command 0x20, data 0x21
• Slave: command 0xA0, data 0xA1

You send Initialization Command Words (ICWs) and Operation Command Words (OCWs) to these ports.

On boot the PIC maps IRQ0-7 onto interrupt vectors 8-15 — which collide with CPU exceptions like the double fault (vector 8). Kernels remap the PIC, typically to vectors 0x20-0x2F, to avoid this clash.

Remapping is an ICW sequence: start init, set the new vector offset, define cascade wiring, set 8086 mode.

The Interrupt Mask Register (IMR) lets you disable individual IRQ lines. Writing a 1 to a bit masks (ignores) that line; 0 enables it.

After servicing an IRQ the handler must send an End Of Interrupt command, or the PIC will not deliver further interrupts on that line.

For IRQ8-15 you must EOI both the slave and the master.

The 8259 design is single-CPU only and supports just 15 lines. It cannot route interrupts to different cores, which makes it useless for SMP systems.

This is why modern hardware moved to the APIC.

The Advanced Programmable Interrupt Controller has two parts:

• Local APIC — one per CPU core, handles the timer and inter-processor interrupts (IPIs)
• I/O APIC — routes external device IRQs to any core

The Local APIC is memory-mapped (default base 0xFEE00000). It provides a per-core timer and lets one core signal another via an IPI through the Interrupt Command Register — essential for waking up cores during boot.

To use the APIC you mask all PIC lines by writing 0xFF to both data ports, then enable the Local APIC via the spurious interrupt vector register. Modern OSes prefer the APIC for multicore scaling.

Test your understanding of the PIC.

You learned how device IRQs reach the CPU:

• The 8259 PIC multiplexes 15 IRQ lines onto one CPU pin
• IRQs are remapped to vectors 0x20-0x2F to avoid exception clashes
• The IMR masks lines; an EOI ends each interrupt
• The APIC replaces the PIC for multicore routing and IPIs