The Programmable Interrupt Controller (PIC) and APIC
Discover how hardware interrupt requests reach the CPU through the 8259 PIC and the modern APIC, including IRQ remapping, masking, and end-of-interrupt signaling.
The Programmable Interrupt Controller (PIC) and APIC is a free Assembly Language & x86 Low-Level Systems Programming lesson on CoddyKit — lesson 4 of 4. You can read the complete lesson below for free — then practise it hands-on in the browser with a built-in code editor and a 24/7 AI tutor. It is part of the Assembly Language & x86 Low-Level Systems Programming learning path, one of 4 lessons in the course, and your progress syncs across the web and the CoddyKit app.
Why a Controller Is Needed
The CPU has only a single hardware interrupt pin (INTR), yet a PC has dozens of devices that need attention. A dedicated chip multiplexes these IRQ lines onto that one pin and tells the CPU which device fired.
That chip is the Programmable Interrupt Controller (PIC).
The Legacy 8259 PIC
The classic PC uses two cascaded 8259A chips, giving 15 usable IRQ lines (IRQ0-IRQ15). The master handles IRQ0-7, the slave IRQ8-15 connected through IRQ2.
- IRQ0 = system timer
- IRQ1 = keyboard
- IRQ14/15 = ATA disks
I/O Ports of the PIC
Each PIC is programmed through two I/O ports:
- Master: command
0x20, data0x21 - Slave: command
0xA0, data0xA1
You send Initialization Command Words (ICWs) and Operation Command Words (OCWs) to these ports.
IRQ Remapping
On boot the PIC maps IRQ0-7 onto interrupt vectors 8-15 — which collide with CPU exceptions like the double fault (vector 8). Kernels remap the PIC, typically to vectors 0x20-0x2F, to avoid this clash.
Remapping in Assembly
Remapping is an ICW sequence: start init, set the new vector offset, define cascade wiring, set 8086 mode.
mov al, 0x11 ; ICW1: begin init, expect ICW4
out 0x20, al ; master command
out 0xA0, al ; slave command
mov al, 0x20 ; ICW2: master vector offset 0x20
out 0x21, al
mov al, 0x28 ; ICW2: slave vector offset 0x28
out 0xA1, alMasking Interrupts
The Interrupt Mask Register (IMR) lets you disable individual IRQ lines. Writing a 1 to a bit masks (ignores) that line; 0 enables it.
in al, 0x21 ; read current master mask
or al, 0x02 ; set bit 1 -> mask IRQ1 (keyboard)
out 0x21, al ; write it backEnd of Interrupt (EOI)
After servicing an IRQ the handler must send an End Of Interrupt command, or the PIC will not deliver further interrupts on that line.
For IRQ8-15 you must EOI both the slave and the master.
mov al, 0x20 ; non-specific EOI
out 0x20, al ; tell master we are doneLimitations of the PIC
The 8259 design is single-CPU only and supports just 15 lines. It cannot route interrupts to different cores, which makes it useless for SMP systems.
This is why modern hardware moved to the APIC.
The APIC Architecture
The Advanced Programmable Interrupt Controller has two parts:
- Local APIC — one per CPU core, handles the timer and inter-processor interrupts (IPIs)
- I/O APIC — routes external device IRQs to any core
Local APIC and IPIs
The Local APIC is memory-mapped (default base 0xFEE00000). It provides a per-core timer and lets one core signal another via an IPI through the Interrupt Command Register — essential for waking up cores during boot.
Disabling the PIC for APIC
To use the APIC you mask all PIC lines by writing 0xFF to both data ports, then enable the Local APIC via the spurious interrupt vector register. Modern OSes prefer the APIC for multicore scaling.
mov al, 0xFF
out 0x21, al ; mask all master IRQs
out 0xA1, al ; mask all slave IRQsQuick Check
Test your understanding of the PIC.
Recap
You learned how device IRQs reach the CPU:
- The 8259 PIC multiplexes 15 IRQ lines onto one CPU pin
- IRQs are remapped to vectors 0x20-0x2F to avoid exception clashes
- The IMR masks lines; an EOI ends each interrupt
- The APIC replaces the PIC for multicore routing and IPIs
Frequently asked questions
Is the “The Programmable Interrupt Controller (PIC) and APIC” lesson free?
Yes — the full text of “The Programmable Interrupt Controller (PIC) and APIC” is free to read here on the web, and the Assembly Language & x86 Low-Level Systems Programming course includes 4 lessons in total. To practise it interactively (a built-in code editor and a 24/7 AI tutor) and unlock the rest of the Assembly Language & x86 Low-Level Systems Programming course, upgrade to CoddyKit PRO.
What will I learn in “The Programmable Interrupt Controller (PIC) and APIC”?
Discover how hardware interrupt requests reach the CPU through the 8259 PIC and the modern APIC, including IRQ remapping, masking, and end-of-interrupt signaling. You practise Assembly Language & x86 Low-Level Systems Programming with hands-on code you run directly in the browser, and a 24/7 AI tutor answers your questions as you work through the lesson.
Do I need any experience to start Assembly Language & x86 Low-Level Systems Programming?
No prior experience is required. Assembly Language & x86 Low-Level Systems Programming on CoddyKit is structured for beginners through advanced learners; this is — lesson 4 of 4, so you can start here or from the beginning and move at your own pace.
How long does the “The Programmable Interrupt Controller (PIC) and APIC” lesson take?
Most CoddyKit lessons take about 5–10 minutes. Each one is bite-sized and interactive, so you make steady progress and pick up exactly where you left off across the web and the app.
Can I write and run code in this Assembly Language & x86 Low-Level Systems Programming lesson?
Yes. Every Assembly Language & x86 Low-Level Systems Programming lesson includes a built-in code editor, so you write and run real code right in your browser and get instant AI feedback — no local setup required.
All lessons in this course
- Understanding Interrupts and Traps
- Interrupt Descriptor Table (IDT)
- Custom Exception Handlers
- The Programmable Interrupt Controller (PIC) and APIC