Wprowadzenie do zestawów instrukcji SSE/AVX

In this lesson, we'll explore powerful instruction sets designed for parallel processing: SSE and AVX. These extensions allow your CPU to perform the same operation on multiple pieces of data simultaneously.

This technique, called Single Instruction, Multiple Data (SIMD), is crucial for speeding up tasks like graphics rendering, scientific calculations, and video processing.

Imagine you need to add two lists of numbers. A traditional scalar processor adds them one pair at a time:

• 1st number + 1st number
• 2nd number + 2nd number
• ...and so on.

A vector processor (using SIMD) can add multiple pairs in a single instruction, significantly faster for large datasets.

SSE stands for Streaming SIMD Extensions. Introduced by Intel, SSE brought 128-bit wide registers and instructions to x86 processors.

This means an SSE instruction can process 128 bits of data in one go. For single-precision floating-point numbers (each 32 bits), this allows processing four numbers at once.

SSE uses a dedicated set of 16 XMM registers, named XMM0 through XMM15. Each XMM register is 128 bits wide.

• They can hold four 32-bit single-precision floating-point numbers.
• Or two 64-bit double-precision floating-point numbers.
• Or sixteen 8-bit integers.

These registers are separate from the general-purpose registers (like EAX, EBX).

Let's look at a basic SSE instruction: MOVAPS. This instruction moves aligned packed single-precision floating-point values. It loads 128 bits of data from memory into an XMM register.

Try running this example (using NASM syntax for Linux x86-64):

AVX, or Advanced Vector Extensions, is a further enhancement to SIMD processing. AVX expands the SIMD registers to 256 bits, doubling the amount of data processed per instruction compared to SSE.

AVX also introduced a new instruction encoding scheme (VEX prefix) and non-destructive operations, meaning destination registers don't overwrite source registers by default.

AVX introduced 16 new YMM registers (YMM0 through YMM15). Each YMM register is 256 bits wide.

• A YMM register can hold eight 32-bit single-precision floats.
• Or four 64-bit double-precision floats.

The lower 128 bits of each YMM register overlap with the corresponding XMM register (e.g., the lower half of YMM0 is XMM0).

The AVX equivalent of MOVAPS is VMOVAPS. The 'V' prefix indicates a VEX-encoded AVX instruction. This instruction moves aligned packed single-precision floating-point values, but now 256 bits at a time.

Here's an example demonstrating loading 8 floats into a YMM register:

While both SSE and AVX are SIMD extensions, AVX offers significant advancements:

• Register Size: SSE uses 128-bit XMM registers; AVX uses 256-bit YMM registers.
• Data Throughput: AVX can process twice as much data per instruction as SSE.
• Non-Destructive Ops: Many AVX instructions allow a three-operand format, keeping source operands intact.
• VEX Prefix: AVX instructions use a VEX prefix, enabling more flexible encoding and future extensions.

Which of the following statements about SSE and AVX registers are TRUE?

We've introduced SSE and AVX, powerful SIMD instruction sets that allow your CPU to perform operations on multiple data items simultaneously. You learned about:

• The concept of SIMD and its benefits for parallel processing.
• SSE with its 128-bit XMM registers (XMM0-XMM15).
• AVX with its 256-bit YMM registers (YMM0-YMM15).
• Basic data movement instructions like MOVAPS and VMOVAPS.

Understanding these instruction sets is key to optimizing performance for data-intensive tasks.